1. Field
This disclosure relates generally to integrated circuit fabrication, and more specifically, to integrating Non-Volatile Memory (NVM) circuitry with logic circuitry in fabricating integrated circuit designs.
2. Related Art
In the field of integrated circuit design, System-on-chip (SoC) devices are commonly used. The term “SoC” refers to devices that integrate several types of blocks, including logic, programmable parts, I/O, volatile memory and non-volatile memory on a single integrated circuit.
Floating-gate based memories are frequently used as non-volatile memories in SoC designs. To overcome the scaling limitations of floating-gate based memories embedded on SoC, thin film storage (TFS) memories are currently being used. In a TFS memory, charge is stored in a thin insulating film consisting of silicon crystals commonly known as nanocrystals.
Integration of TFS (Thin Film Storage) memories with logic circuitry in an SoC requires two gate etches, one for a select gate in the TFS area and another for the gate of logic or peripheral transistors in the logic area. The logic or peripheral transistors are very small, having critical dimensions, and are thus complicated to pattern. In one approach, gates of tiny transistors are patterned using a bottom anti-reflective coating (BARC) layer which is deposited over the gate oxide to achieve critical dimension (CD) control of gate dimensions of the transistors. Since a BARC has high viscosity, it is difficult to deposit BARC layers. Further, the process gets more complicated if there is a difference in height between the memory area and logic area on the SoC. In addition, if the physical distance between the memory area and the logic area on the SoC is small, a very thick layer of non-planar BARC gets deposited over the gate oxide in the logic area which is difficult to etch. In addition, the patterning of a transistor gate using the thick BARC layer is a complicated process, as the thick BARC layer is too anti-reflective. To resolve this non-planarity problem, the distance between the memory area and the logic area, called isolation region, is required to be large. However, an increase in the isolation region entails layout inefficiencies in the SoC design.
Another approach for patterning a small-dimensioned transistor includes deposition of a regular anti-reflective coating (ARC) or nitride. However, it is difficult to etch it in the later processes due to the non-planarity problem.
There exists a need for a method to overcome these problems and to reduce the process complexity while integrating the NVM circuitry with the logic circuitry in the SoC.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.